module digital_tube
#(
   parameter CNT_100MS_MAX = 50000
)
(
    input clk,
    input rst_n,
    input [3:0] din_d0,
    input [3:0] din_d1,
    input [3:0] din_d2,
    input [3:0] din_d3,
    input [3:0] din_d4,
    input [3:0] din_d5,
    input [5:0] din_dp,
    output reg [5:0] dout_sel,
    output reg [7:0] dout_dig
    );

    localparam CNT_DN_MAX = 6;//数码个数

	localparam
    NUM0 = ~8'h3f,
    NUM1 = ~8'h06,
    NUM2 = ~8'h5b,
    NUM3 = ~8'h4f,
    NUM4 = ~8'h66,
    NUM5 = ~8'h6d,
    NUM6 = ~8'h7d,
    NUM7 = ~8'h07,
    NUM8 = ~8'h7f,
    NUM9 = ~8'h6f,
    NUMA = ~8'h77,
    NUMB = ~8'h7c,
    NUMC = ~8'h39,
    NUMD = ~8'h5e,
    NUME = ~8'h79,
    NUMF = ~8'h71;

	reg out_dp;
	reg [3:0] in_hex;

	reg[15:0] cnt_1ms;
    wire  cnt_1ms_end;
	wire cnt_1ms_add;

    reg[15:0] cnt_dn;
    wire cnt_dn_end;
	wire cnt_dn_add;


    assign cnt_1ms_add = 1;
    assign cnt_1ms_end = cnt_1ms_add && cnt_1ms== CNT_100MS_MAX-1;

    assign cnt_dn_add= cnt_1ms_end;
    assign cnt_dn_end= cnt_dn_add &&  cnt_dn == CNT_DN_MAX - 1;

	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			cnt_1ms <= 0;
		end
		else if(cnt_1ms_add)begin
			if(cnt_1ms_end)
				cnt_1ms <= 0;
			else
				cnt_1ms <= cnt_1ms + 1;
		end
	end

	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			cnt_dn<=0;
		end
		else if(cnt_dn_add)begin
			if(cnt_dn_end)
				cnt_dn <= 0;
			else
				cnt_dn <= cnt_dn + 1;
		end
	end



	always@(*) begin
		case(cnt_dn)
            3'b000:begin
                dout_sel = 6'b111110; //选中第1个数码管
                in_hex = din_d0;
                out_dp = din_dp[0];
            end
            3'b001:begin
                dout_sel = 6'b111101; //选中第二个数码管
                in_hex = din_d1;
                out_dp = din_dp[1];
            end
            3'b010:begin
                dout_sel = 6'b111011;
                in_hex = din_d2;
                out_dp = din_dp[2];
            end
             3'b011:begin
                dout_sel = 6'b110111;
                in_hex = din_d3;
                out_dp = din_dp[3];
            end
            3'b100:begin
                dout_sel = 6'b101111;
                in_hex = din_d4;
                out_dp = din_dp[4];
            end
            default:begin
                dout_sel = 6'b011111;
                in_hex = din_d5;
                out_dp = din_dp[5];
            end
		endcase
	end


	always@(posedge clk) begin
		case(in_hex)
			4'h0: dout_dig[7:0] <= NUM0;
			4'h1: dout_dig[7:0] <= NUM1;
			4'h2: dout_dig[7:0] <= NUM2;
			4'h3: dout_dig[7:0] <= NUM3;
			4'h4: dout_dig[7:0] <= NUM4;
			4'h5: dout_dig[7:0] <= NUM5;
			4'h6: dout_dig[7:0] <= NUM6;
			4'h7: dout_dig[7:0] <= NUM7;
			4'h8: dout_dig[7:0] <= NUM8;
			4'h9: dout_dig[7:0] <= NUM9;
			4'ha: dout_dig[7:0] <= NUMA;
			4'hb: dout_dig[7:0] <= NUMB;
			4'hc: dout_dig[7:0] <= NUMC;
			4'hd: dout_dig[7:0] <= NUMD;
			4'he: dout_dig[7:0] <= NUME;
			default: dout_dig[6:0] = 7'b0111000;
		endcase
		dout_dig[7] = out_dp;
	end
endmodule